FPGA Design Services

Logic Design, Board Design and Bring-Up in One Engagement

Service Overview

FPGA and CPLD design services covering Verilog/VHDL logic design, timing closure, high-speed board design and bring-up. Delivered on Lattice LCMXO2, Microchip PolarFire MPF100T and Altera EPM240/EPM570.

XTELL delivers FPGA design services covering logic design, board design and bring-up as a single engagement. We work across Lattice, Microchip, AMD/Xilinx and Altera device families and their vendor toolchains — Diamond, Libero, Vivado and Quartus — and our projects typically involve both the RTL and the PCB it runs on, which is where most FPGA projects actually get into trouble.

Recent silicon we have shipped on includes the Lattice LCMXO2-4000HC-4MG132 in a long-distance fibre signal board, the Microchip PolarFire MPF100T on a custom core board, and Altera EPM240 and EPM570 CPLDs implementing print timing logic. On the fibre board the FPGA drives high-speed ADC and DAC paths alongside a Maxim DS4835 optical transceiver, with automatic gain control, digital filtering and signal recovery implemented in Verilog.

Because FPGA boards live or die on signal integrity, we treat impedance matching, return paths and EMC as part of the logic engagement rather than a separate PCB job. Bit error rate testing, optical power measurement and oscilloscope-based timing validation are part of what we hand over, not an extra line item.

For teams evaluating a new device, we also build reference-design-based core boards. The PolarFire MPF100T board was laid out from the Microchip evaluation kit schematics, with pin assignment driven by official datasheets and FSI/Type-C reference material guiding the high-speed interfaces.

Not every project needs an FPGA. Where the logic is small and fixed, CPLD design services are cheaper, boot instantly and draw far less power — the EPM240 and EPM570 print controller is a deliberate example of choosing the smaller device. We provide Verilog design services and VHDL work on either class of part, and will say plainly when a microcontroller would do the job that an FPGA is being considered for. Choosing the smallest part that meets the requirement is usually the difference between a board that reaches production and one that stalls on cost. Where an existing design needs migrating between vendors, we handle the RTL port and the constraint rewrite together, since a device change almost always moves the timing problem rather than removing it.

Service Features

Device selection and resource analysis

Verilog / VHDL logic design

Timing constraint definition and closure

Carrier and core board design

High-speed signal integrity design

BER and timing validation on hardware

Technology Stack

Lattice: LCMXO2-4000HC-4MG132, MachXO2 family

Microchip: PolarFire MPF100T

Altera/Intel: EPM240, EPM570, MAX2 CPLD

Languages and tools: Verilog, VHDL, vendor toolchains (Vivado / Quartus / Libero / Diamond)

Signal chain: high-speed ADC/DAC, LNA, Maxim DS4835 optical transceiver

Validation: oscilloscope timing, BER testing, optical power measurement

Related Project Cases

Lattice Fiber Signal Communication Board

Lattice LCMXO2-4000HC-4MG132 driving high-speed ADC and DAC paths with a Maxim DS4835 optical transceiver. AGC, digital filtering and signal recovery in Verilog, validated with BER and optical power testing.

PolarFire FPGA Core Board

Microchip PolarFire MPF100T core board laid out from official evaluation kit schematics, with datasheet-driven pin assignment and FSI/Type-C reference for the high-speed interfaces.

CPLD Print Control Board

Altera EPM240 and EPM570 CPLDs implementing print timing logic, with multi-version PCB iteration to optimise signal integrity.

What You Receive

Verified RTL implementation with testbench results

Synthesis and timing closure reports

Pin assignment and constraint files

Carrier board design documentation

GERBER and full production file set

Bring-up report with BER and timing measurements

Programming files and flashing procedure

How We Work

Device selection

Logic resource, I/O count, transceiver and power budget analysed against the application.

RTL design

Verilog or VHDL implementation with testbench-driven functional verification.

Board design

Carrier or core board layout with impedance control on all high-speed paths.

Timing closure

Constraint refinement and synthesis iteration until timing targets are met.

Bring-up & validation

Oscilloscope timing checks, BER testing and optical power measurement where applicable.

Frequently Asked Questions

Which FPGA families do you work with?

Lattice MachXO2 including the LCMXO2-4000HC-4MG132, Microchip PolarFire up to the MPF100T, Altera MAX II CPLDs such as the EPM240 and EPM570, and AMD/Xilinx Zynq-7000. We work in the corresponding vendor toolchains - Diamond, Libero, Quartus and Vivado. Device selection is part of the engagement when the target is not yet fixed.

Do you deliver RTL only, or the board as well?

Both, and we prefer both. Most FPGA problems surface at the boundary between logic and board — clock distribution, return paths, power integrity. Splitting those across two vendors is where schedules go wrong.

How is timing closure verified?

Synthesis and static timing reports are delivered with the constraint files, and we validate on hardware with oscilloscope timing captures. For signal-chain projects we add bit error rate testing and, on optical links, optical power measurement.

Can you build a core board from a vendor evaluation kit?

Yes — that is how the PolarFire MPF100T board was built. We work from the official evaluation kit schematics, drive pin assignment from the datasheets, and follow vendor reference material for high-speed interfaces.