FPGA Design ServicesLogic, Timing and the Board
Verilog/VHDL, timing closure and high-speed board design on Lattice, PolarFire and CPLD. Shenzhen, since 2016.
Service Overview
FPGA and CPLD design services covering Verilog/VHDL logic design, timing closure, high-speed board design and bring-up. Delivered on Lattice LCMXO2, Microchip PolarFire MPF100T and Altera EPM240/EPM570.
XTELL provides FPGA design services: Verilog/VHDL logic design, timing closure and high-speed board design, across Lattice, Microchip PolarFire and CPLD.
Who this FPGA design service is for
• Teams whose high-speed acquisition or real-time signal processing has outrun the MCU: the software cannot keep up with the sample rate, and an FPGA needs to take over the hard real-time part.
• Equipment makers who need precise timing: printing and motion control run many channels in parallel at nanosecond resolution, and a software loop will never hold it.
• Clients who need an FPGA board taken from logic to hardware: an engagement that writes HDL without owning the board falls apart at the high-speed interfaces.
• Clients with an existing FPGA project to take over or improve: timing will not close, resources are over budget, versions are in disarray, and someone needs to pick it up and carry it forward.
The FPGA and CPLD platforms we have delivered on
Three delivered projects cover three device classes: the Lattice LCMXO2 family (LCMXO2-4000HC-4MG132, fibre signal processing), Microchip PolarFire (the MPF100T core board) and Intel CPLDs (EPM240 and EPM570, print timing control). Lattice MachXO2 suits small-to-mid glue logic and signal processing; PolarFire targets high density and high-speed interfaces; CPLDs handle small, deterministic timing logic. Devices are chosen for the requirement, not from what is in stock.
Case one: the Lattice-based fibre signal communication board
This board is a complete example of taking an FPGA from logic through the whole signal chain. A Lattice LCMXO2-4000HC-4MG132 FPGA does the signal processing and a Maxim DS4835 handles the optical transceiver; the signal chain includes a high-speed ADC, a high-speed DAC, an LNA and signal conditioning circuitry. On the FPGA side, Verilog/VHDL implements the logic and timing control, with automatic gain control (AGC), digital filtering and signal recovery; the system layer runs FreeRTOS. The challenge was fighting attenuation and signal distortion over long fibre runs while staying stable at a high sample rate. Verification used an oscilloscope, an optical power meter and bit error rate testing, and an adaptive master-slave mechanism made networking more flexible.
Case two: the PolarFire FPGA core board
The challenge on the PolarFire FPGA core board (MPF100T) was high-speed signal routing and power integrity. The PCB design follows the schematics of Microchip's official evaluation kit, pin assignment follows the official datasheets, and FSI and Type-C reference material guided the high-speed interfaces. The honest lesson of a core board: the official reference design is a starting point, not a constraint - but every departure from it, whether in layer count, power tree or interface breakout, needs a clear reason, or it gets paid back double during debugging.
Case three: the printer control hardware system
The printer control hardware system uses CPLDs for precise print timing. The challenges were timing accuracy and compatibility across hardware versions. EPM240 and EPM570 CPLDs implement the print timing logic, multi-version PCB iteration improved signal integrity, and a MAX II device extends the functionality. Print head firing runs in parallel at microsecond resolution, a determinism software cannot provide - exactly the job a CPLD is for: small logic, deterministic timing, working the moment power is applied.
Timing closure is the dividing line in an FPGA project
Between simulating and running on the board sits timing closure: are clock-domain crossings synchronised, do the constraints reflect real board timing, has routing congestion been broken up? On the fibre board, the high-sample-rate ADC and DAC paths are extremely sensitive to timing margin, and closure is not done when the compiler reports green - it has to pass stably across real temperatures and device variation. XTELL's delivery standard is stable measured behaviour on the board, not a passing simulation.
High-speed board design: the FPGA cannot be discussed apart from the board
The board sets an FPGA's performance ceiling. If power integrity cannot hold the core voltage through a dip, perfect timing is worthless; if high-speed traces are not impedance-controlled, the eye closes. The fibre board's PCB design includes impedance matching and EMC design, iterated alongside the logic. That is why XTELL keeps FPGA logic and PCB design in one team - when logic engineers and board engineers collaborate across a company boundary, locating a problem takes an extra lap.
When a CPLD fits better than an FPGA
Not every programmable logic need calls for an FPGA. CPLDs suit small logic - deterministic tasks like print timing - instant-on operation with no configuration load, and cost-sensitive designs. The printer control system used the EPM240 and EPM570 on exactly this judgement: deterministic timing and a simple structure, where an FPGA would be waste. The opposite cases - high density, high-speed interfaces, algorithm processing - are what justify a device like PolarFire. The honest rule: enough capacity is enough, and nobody should pay for a device name on a résumé.
Verification uses real instruments, not simulation alone
FPGA verification has to reach the instruments. The fibre board's verification chain was an oscilloscope for signal quality, an optical power meter to confirm the optical link budget and bit error rate testing (BER) for communication quality. Simulation covers functional correctness; instruments cover the physical world's imperfections - jitter, attenuation, crosstalk and temperature drift. Before delivery the standard is instrument data, and every conclusion in the acceptance documents is backed by a measurement.
Vendor toolchains: Diamond, Libero and Quartus
FPGA development uses the vendor toolchains: Libero for Microchip PolarFire, Vivado for Xilinx (AMD), Diamond for Lattice devices and Quartus for Intel CPLDs. Vendor toolchains have no substitutes, and that is the reality of the industry. Porting logic from one vendor family to another is assessed per project; the deeper the binding to vendor IP and primitives, the higher the cost of porting, and that is spelled out at the design stage.
FPGA, firmware and upper software in one team
On the fibre board, the FPGA logic, the FreeRTOS system layer and the signal algorithms - AGC, digital filtering and signal recovery - were delivered by one team. The value of that structure is that the FPGA-to-software interface - register map, interrupts and DMA semantics - is defined and implemented by the same people, so integration never turns into a cross-vendor standoff where the logic says it delivered the data and the software says it received nothing. Diagnosis that crosses layers is what separates XTELL from logic-only outsourcing teams.
How we work together and how delivery scope is agreed
1. Requirements review: share signal chain specifications, timing requirements or the existing project, and we settle device selection and architecture.
2. Proposal and contract: logic architecture, verification plan and milestones are written down. Whether HDL source and design files are delivered, and under an open or closed model, is agreed item by item in the contract. Nothing on this page constitutes a blanket commitment.
3. Development and verification: logic design, board integration and instrument measurement, with multi-version iteration tracked in records.
4. Delivery: scope follows the contract. Timeline and price are given after assessment; this page does not fix numbers.
About XTELL
XTELL (Shenzhen XTELL Future Technology) was founded in Shenzhen in 2016. Over the ten years since, it has delivered more than 100 projects, with clients predominantly western B2B companies. Its work covers every layer from circuit board to cloud: PCB design, FPGA, embedded firmware, Linux BSP, device interfaces, mobile apps, backends and IoT platforms.
Service Features
Technology Stack
Related Project Cases
Lattice Fiber Signal Communication Board
Lattice LCMXO2-4000HC-4MG132 driving high-speed ADC and DAC paths with a Maxim DS4835 optical transceiver. AGC, digital filtering and signal recovery in Verilog, validated with BER and optical power testing.
PolarFire FPGA Core Board
Microchip PolarFire MPF100T core board laid out from official evaluation kit schematics, with datasheet-driven pin assignment and FSI/Type-C reference for the high-speed interfaces.
CPLD Print Control Board
Altera EPM240 and EPM570 CPLDs implementing print timing logic, with multi-version PCB iteration to optimise signal integrity.
What You Receive
Frequently Asked Questions
Which FPGA vendors do you use?
Delivered projects: Lattice LCMXO2 (the fibre signal board), Microchip PolarFire MPF100T (the core board) and Intel CPLD EPM240/EPM570 (print timing control), using the vendor toolchains Diamond, Libero and Quartus. Other families are assessed per project - the methodology carries over, but IP and primitive bindings have to be checked item by item.
Our design will not close timing. Can you take it over and rescue it?
We can take it over after assessment. We first check whether the constraints reflect real board timing and whether clock-domain crossings are synchronised, then judge whether it is an architecture problem or an implementation one - architectural failures sometimes mean changing the module partitioning, which no constraint change will fix. The assessment and a work estimate come together, and whether and how we take it on is settled before signing.
Do you also design the PCB for the FPGA board?
Yes. The fibre signal board and the PolarFire core board were both delivered with logic and board together, and the PCB design covers impedance matching and EMC, done in KiCad. The lesson from high-speed FPGA work: split logic and board between teams and the time saved gets paid back double at integration.
Do you deliver the HDL source?
We work under both open and closed models. Whether HDL source and design files are part of the delivery, and how they are licensed, is agreed per project in the contract and written down before signing. This page makes no blanket commitment; tell us your preferred model at the quoting stage.
Do you work with Xilinx / AMD devices?
Yes, Xilinx (now AMD) devices are part of our delivered work, alongside Microchip PolarFire, Lattice and Intel CPLD. Development runs in Vivado, and device selection follows the requirement: logic capacity, high-speed interfaces, power and availability are weighed together rather than defaulting to one vendor.
Our FPGA product needs FCC / CE certification. Do you support that?
Yes. Clients' products routinely need FCC or CE certification, and XTELL handles the design work certification depends on: EMC-related layout decisions around high-speed interfaces, the firmware and hardware builds needed for testing, and the documentation the lab requires. Certificates are issued by accredited test labs.
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