Embedded Hardware Design: From Core Boards to Production-Ready PCBs

Hardware Design Is Risk Management

Every embedded hardware project is a bet placed months before the payoff. Unlike software, you cannot patch a PCB with a deploy — a wrong footprint, a missed decoupling capacitor, or an antenna placed next to a switching regulator becomes a board spin, and each spin costs weeks and thousands of dollars. Good embedded hardware design is therefore not primarily about clever circuits; it is about systematically removing risk before the Gerbers go to the fab.

We have designed production hardware across the complexity spectrum — Rockchip application-processor mainboards, Allwinner custom motherboards, dual-version consumer devices, power management boards. This guide distills the decisions that separate boards that work the first time from boards that become expensive coasters.

Core Board or Full Custom: The First Fork

Almost every project faces this choice: start from a vendor core board (system-on-module) or design the full board from scratch.

We have done both, repeatedly. The Rockchip core board program (RK_CORE) produced core board designs for both RK3128 and RK3568, iterating from V1.0 to V1.7 with revision suggestion documents and cost analysis at each step. The dual-RK3566 board (dual_rk3566) went further — two RK3566 chips on one board with fixed perimeter screw holes, a central heatsink mounting area, an XT30 power connector, and a UVC camera sub-project (SN9C2726 + GC2083 over MIPI).

The decision framework we use:

• Use a core board when time-to-market dominates, volumes are in the hundreds to low thousands, or the application processor's BGA fanout and DDR routing exceed your team's current experience. The vendor already solved the hardest 20% of the layout.
• Go full custom when the form factor is the product (wearables, compact sensors), unit cost at volume justifies the NRE, or you need integration no module offers. The RK3128 mainboard project (nucleic_detector) went full custom with multi-version PCB design, complete Gerber output, LCD driver board, and debugging notes — because the product needed exactly that shape and exactly those connectors.
• The hybrid path — custom carrier board plus compute module — is underrated. You get the processor complexity pre-solved and keep full control of I/O, power, and mechanics.

Iteration Discipline: Plan for Three Spins, Aim for One

Nothing reveals hardware maturity like version history. The Allwinner T113 custom motherboard (t113_mipi) went from V1 through V1.2 with MIPI interface boards for 5-inch and 7-inch screens, each version carrying complete PCB design, schematics, and contract documents. The RK3568 core board iterated V1.0 to V1.7. These are not signs of failure — they are the normal, healthy rhythm of hardware development.

What separates professional iteration from flailing is what each spin is for:

• Spin 1 (EVT — engineering validation): prove the architecture. Does it boot? Do the interfaces work? Expect bodge wires; the goal is answering unknowns, not beauty.
• Spin 2 (DVT — design validation): prove the design. Signal integrity measured, thermal validated, EMC pre-scanned. This is where the revision suggestion documents earn their keep.
• Spin 3 (PVT — production validation): prove manufacturability. Built on the actual production line, with the actual test fixture.

Budget and schedule for three spins; celebrate when you ship on two. Teams that plan for one spin inevitably do three anyway — just late and panicked. Keep a written spin log: what changed, what it fixed, what it broke. Six months later, that log is the most valuable document in the project.

Power Integrity: The Silent Killer

Ask experienced hardware engineers what kills boards most often and power integrity tops the list. Application processors like the RK3568 have aggressive power sequencing requirements — get the rail order wrong and the chip latches up or simply never boots reliably. High-current paths (the XT30 connector on the dual-RK3566 board exists because the current demands are real) need copper width calculated, not guessed.

Our checklist for every design: power tree documented rail by rail with sequencing; decoupling capacitors placed per the chip vendor's guidelines before routing begins; PDN impedance considered for anything with DDR; and every regulator's thermal path verified — a regulator that works on the bench in winter fails in a sealed enclosure in summer. The oven control PCB project (oven_pcb), with its Buck-Boost power stages and touch/LCD subsystems, is a reminder that power design is a first-class citizen, not a footnote to the digital design.

Signal Integrity: Measure Twice, Route Once

DDR routing, MIPI display interfaces, USB — modern embedded boards carry signals that do not forgive sloppy layout. The T113 project's MIPI boards for 5-inch and 7-inch screens demanded length-matched differential pairs; the RK3128 mainboard's LCD driver board the same. Rules we enforce:

• High-speed interfaces get their routing constraints before the rest of the board is placed — they are the prima donnas that get first pick of layers and space.
• Reference planes stay continuous under high-speed traces. A trace crossing a plane split is an antenna and a signal integrity problem wearing the same clothes.
• Every high-speed interface gets a bring-up test point or connector. You cannot debug what you cannot probe.

Designing for Two Versions at Once

The dual-version thermometer gun hardware (ThermoGun) — A and B hardware versions with DSN/PCB for each, four working modes, backlight and housing design — illustrates a common commercial reality: one product, multiple SKUs. The professional approach is a shared core schematic with variant assemblies: same PCB, different BOM options, version detection in firmware. Designing the variants as separate projects doubles the validation work; designing one board with controlled variants keeps a single spin fixing both.

The Manufacturing Handoff: Gerbers Are Not Enough

A design is not done when the layout is done. The production-ready package we deliver — and what the thermometer gun production solution (LandwinGUN) exemplifies — includes Gerber files, silkscreen, pick-and-place coordinates, stencil files, and the assembly drawings the factory actually builds from. Missing pick-and-place data means the SMT line operator guesses rotations; guessed rotations mean tombstoned components.

Equally important: the battery management system PCB (AD_PCB, BCMU/BMU core boards for an energy customer) shipped with schematics, PCB, pick-and-place, and Gerbers as a complete, self-consistent set. Self-consistency is the key word — every file generated from the same layout revision, versioned together. The number-one manufacturing defect source we see is not bad design but file mismatch: Gerbers from Tuesday, pick-and-place from Thursday.

Component Selection: Availability Is a Specification

The 2021–2023 chip shortage taught the industry a lesson that should never be unlearned: availability is a component specification, right alongside voltage and temperature range. A perfect part with a 52-week lead time is not a part — it is a schedule risk. Our selection discipline now includes: preferring parts with at least two authorized distributors showing stock, checking the manufacturer's longevity program (automotive/industrial-grade parts tend to live longer), and designing in second-source alternatives for passives, connectors, and regulators from day one.

For single-source critical parts — the SoC, the radio module — we qualify the alternative before we need it. The USB Type-C development board project (usb_type_c_board), which replaced the MUX device on a Type-C PD controller reference board with an alternative part and designed dual-port and single-port variants, is exactly this muscle: the ability to swap a critical component and re-verify without redesigning the product. Teams that can second-source quickly survive shortages; teams that cannot, wait.

DFM Details That Save a Spin

Beyond the headline disciplines, a collection of small design-for-manufacturing details separates one-spin boards from three-spin boards. Component packages: prefer packages your assembly house places every day — exotic packages mean exotic problems, from moisture sensitivity to tombstoning. Fiducials: place three global fiducials and local fiducials near fine-pitch parts; the pick-and-place machine's vision system depends on them. Panelization: design the panel with the fab, not after — V-score vs. tab routing affects edge clearance and depaneling stress on nearby components.

Testability deserves its own line item. Every board we ship includes a programming/debugging header (SWD, JTAG, or UART bootloader pins) accessible without disassembly, plus test points on power rails so the factory can verify voltages during ICT. The cost is a few square millimeters; the payoff is a factory that can actually test what you designed. Boards that cannot be programmed or probed without surgery become expensive problems the moment anything goes wrong in production.

Conclusion

Embedded hardware design rewards the paranoid: choose the core-board-vs-custom tradeoff deliberately, plan three spins, treat power integrity as the main event, route high-speed signals first, design variants as one board, and hand manufacturing a complete, version-locked package. Do that and the fab sends back boards that boot.

If you need production hardware designed — from core boards to full-custom mainboards — our hardware design service has shipped exactly this range. For the schematic-to-PCB process detail, see our hardware design process guide; for getting to testable hardware fast, see rapid hardware prototyping.