hardware design

    Hardware Design Process: From Schematic to Production-Ready PCB

    The end-to-end hardware design flow we follow — schematic capture, multi-version PCB iteration, and signal integrity — illustrated with three real board designs.

    ·XTELL Engineering Team

    Why the Hardware Design Process Matters

    Most hardware failures are not discovered on the production line — they are decided there. By the time a board reaches fabrication, the vast majority of its cost, reliability, and performance characteristics have already been locked in by decisions made during schematic capture, component selection, and layout. A disciplined hardware design process does not guarantee a perfect first spin, but it does guarantee that every spin teaches you something measurable, and that the distance between the first prototype and a production-ready PCB is a planned journey rather than a scramble.

    At XTELL, our hardware development services follow the same end-to-end flow on every project: requirements and component selection, schematic discipline, PCB layout and iteration, signal and power integrity review, verification, and handoff to production. The flow is the same whether the board is a small sensor module or a complex FPGA carrier — what changes is how much rigor each stage demands. This article walks through that flow, illustrated with three real board designs we have delivered: a USB Type-C development board, a multi-version gas sensor module, and a Microchip PolarFire FPGA core board.

    Requirements and Component Selection

    Every board starts with a requirements document that answers three questions: what the board must do, what environment it must survive, and what constraints it must respect. From those answers comes the most consequential decision of the entire project — component selection. Choosing the wrong part early can force a board re-spin later, while choosing the right alternative part can rescue a schedule.

    Our USB Type-C development board project is a good example. The board was an interface-solution verification platform built around a Type-C PD controller reference design. The challenge was component availability and reliability: the MUX device used on the reference board needed to be replaced with an alternative part. A MUX replacement in a USB Type-C signal path is not a simple swap — the replacement must preserve signal integrity on the high-speed lanes while behaving correctly under PD controller negotiation.

    Our approach was to design two variants in parallel: a dual-port board and a single-port board, both using the alternative MUX device, and to verify each against the reference design by direct comparison. Running the comparison against a known-good reference meant we could isolate the behavior of the replacement part from everything else in the system. The dual-port design let us validate multi-port arbitration and power delivery behavior; the single-port design gave us a simpler platform where any signal-integrity issue could be attributed cleanly to the new MUX or its routing. This kind of comparative verification during component selection pays for itself many times over — it is far cheaper to qualify a replacement part on a development board than to discover a problem after it is designed into a shipping product.

    What Component Selection Covers

    • Confirming that candidate parts meet the functional, electrical, and mechanical requirements of the design.
    • Checking availability, lead time, and lifecycle status — a perfect part that cannot be sourced is not a perfect part.
    • Verifying that replacement or alternative parts behave like the originals, using comparison testing against a reference design where one exists.
    • Documenting the rationale so that future revisions, and the production team, understand why each part was chosen.

    Schematic Discipline

    The schematic is the contract between the design intent and the physical board. A disciplined schematic does more than connect pins — it communicates. Net names carry meaning, power domains are clearly separated, and review checkpoints are explicit rather than improvised.

    Our schematic discipline rests on a few principles that have survived every project:

    • Readable before routable. If a reviewer cannot trace a signal path by reading the schematic, the layout engineer will not be able to route it correctly either. Hierarchical sheets, consistent net naming, and explicit connectors between blocks are non-negotiable.
    • Datasheet-driven pin assignment. Pin assignments are never improvised. On FPGA projects in particular, every pin is assigned against the official datasheet and documented with its intended function, bank, and voltage domain before layout begins.
    • Review gates, not review hopes. A schematic passes through formal review — by a second engineer, against the requirements, and against the component documentation — before a single trace is drawn. Errors caught at schematic review cost minutes; errors caught at first article inspection cost weeks.
    An hour spent reviewing a schematic saves a spin of the board. There is no cheaper insurance in hardware development.

    PCB Layout and Iteration

    Layout is where the schematic's intent meets physical reality: component placement, layer stackup planning, routing discipline, and manufacturability checks all happen here. Our PCB design services treat the first layout as a hypothesis and the review process as the test.

    The gas sensor module project shows why iteration is a feature, not a failure. Gas sensors place demanding requirements on both precision and power: the analog front end must be sensitive enough to detect small signal changes, while the power circuitry must deliver clean, stable rails without contaminating those same signals. Meeting both requirements across different application scenarios could not be done in a single pass, so the project was deliberately structured as a multi-version effort.

    The first revision, SENSOR2-1105A, established the baseline architecture — schematic and PCB captured in EDA tools, with the sensor and its signal conditioning circuits placed and routed. Testing of that revision identified where the layout and the conditioning circuitry could be improved. The next major revision, X_Sensor_V2-1119C, incorporated those learnings: the sensor layout was optimized and the signal conditioning circuits were refined to better serve the precision and power requirements across the target application scenarios. Each version was a complete, testable artifact, and the delta between versions was a record of engineering decisions, not guesses.

    What Each Layout Iteration Should Deliver

    • A testable board that answers specific questions left open by the previous revision.
    • Documented deltas — what changed, why it changed, and what it is expected to fix or improve.
    • Verified manufacturability: footprint correctness, assembly clearances, and test access.
    • A decision record that feeds the next revision or the production release.

    Multi-version iteration only works when the versions are honest. A revision that changes ten things at once teaches you nothing about which change mattered. We keep each spin focused, so the board gets simpler to understand with every version, not just smaller or cheaper.

    High-Speed and Signal-Integrity Notes

    As designs move from sensor modules to high-speed digital systems, layout stops being primarily a geometry problem and becomes a physics problem. High-speed signal routing and power integrity are where FPGA boards are won or lost, and they cannot be bolted on after the fact — they have to be designed in from pin assignment onward.

    Our PolarFire FPGA core board, built around the Microchip PolarFire MPF100T, illustrates the approach. The core board's challenge was exactly this: routing high-speed signals cleanly while maintaining power integrity across the FPGA's multiple supply domains. Our solution was deliberately conservative and documentation-driven. We referenced Microchip's official evaluation kit schematics as the proven baseline for the FPGA's support circuitry, used the official datasheets to guide pin assignment for the MPF100T itself, and drew on FSI and Type-C reference materials for the high-speed interface portions of the design.

    The deliverables reflected that discipline: complete PCB design files and schematics, the reference designs and evaluation kit schematics we worked from, and the official datasheets — a full paper trail from requirement to routing decision. When a high-speed interface misbehaves on the bench, the first question is always whether the design followed the reference; having the references embedded in the project documentation makes that question answerable in minutes.

    Signal-Integrity Habits That Scale

    • Pin assignment guided by the datasheet and the evaluation kit, documented before layout.
    • Power domains planned as carefully as signal paths — an FPGA's supplies are part of the signal chain.
    • Reference designs treated as a starting baseline to be understood, not copied blindly.
    • High-speed interfaces designed against proven reference material, such as the FSI and Type-C references used on the PolarFire board.

    Verification and Handoff to Production

    A board is not production-ready when it powers on — it is production-ready when it can be built repeatedly, tested efficiently, and supported in the field. Our verification flow has three layers.

    First, functional verification against the requirements: does the board do what the requirements document asked for? For the USB Type-C boards, this meant comparison testing against the reference design to confirm the alternative MUX device behaved correctly in both single-port and dual-port configurations. For the gas sensor module, it meant confirming that the revised sensor layout and signal conditioning met the precision and power requirements of the target scenarios.

    Second, stress and margin testing: does the board keep working outside the nominal case? Power rails are checked under load, interfaces are exercised at their limits, and environmental margins are confirmed where the application demands them.

    Third, production handoff: the fabrication and assembly package must be complete and unambiguous. That means finalized Gerbers and drill files, a clean bill of materials with approved alternates documented, assembly drawings, and test procedures that the factory can actually execute. A design that cannot be handed off cleanly is not finished — it is just a prototype with ambitions.

    Production readiness is a property of the documentation package, not just the board. If the factory has to guess, the design is not done.

    Conclusion

    Hardware design is a process of progressive commitment: requirements narrow the choices, schematic review locks the intent, layout and iteration converge on a working physical design, signal-integrity discipline protects the high-speed paths, and verification proves the board is ready to be built at scale. None of the three projects described here succeeded because of a single brilliant decision — they succeeded because the same disciplined flow was applied consistently, from the MUX comparison testing on the Type-C boards, through the focused revisions of the gas sensor module from SENSOR2-1105A to X_Sensor_V2-1119C, to the datasheet- and evaluation-kit-driven design of the PolarFire MPF100T core board.

    If you are planning a board that needs to survive this journey — from a first schematic to a product that can be manufactured reliably — our hardware development services cover the full flow, and our PCB design services handle the schematic-to-layout portion in depth. The process is the product, long before the board is.

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